1. Field of the Disclosure
The present disclosure generally relates to packet generation and diagnostics, and more particularly, to systems and methods for test packet generation and diagnostics integrated into circuitry of a packet switching system.
2. Relevant Background
The functionality of integrated circuits such as passive switch chips, passive RFID (radio frequency identification) chips, and memory controllers, to name a few, may be tested before being sold to an external party and/or before being used with a larger system. Testing the functionality may include testing for at least data packet corruption and/or data packet loss. Typically, these types of integrated circuits are not capable of generating packets for testing and are dependent upon receiving packets from an external source, e.g., a CPU (central processing unit). Testing functionality of the integrated circuits absent a CPU can involve the use of external test equipment to generate packets for insertion into passive circuitry. For example, complex test systems and/or various types of logic circuitry (e.g., FPGAs (Field Programmable Gate Arrays)) can be configured to simulate operation of a CPU in a test environment. However, these techniques are often expensive and cumbersome, have limited compatibility with various types of circuitry, have limitations on test speeds, limit the ability to test the circuitry inside its intended operating environment, etc.